The present invention relates to a defect analyzing LSI having memory cells, which is used for periodic monitoring in factories.
Semiconductor products are manufactured through a manufacturing line comprising a series of steps of process, but, for some cause or other in connection with the manufacture, defective semiconductor products are manufactured in some cases. In such a case, it is necessary to clear up the cause for the defect and improve a portion of the process to thereby eliminate the cause for the defect (process feedback) and thus to enhance the manufacturing yield of the semiconductor products. However, in order to analyze the defective semiconductor products and clear up the cause for the defect, very difficult work must be carried out.
Thus, for the purpose of enhancing the manufacturing yield of semiconductor products, there is periodically manufactured an LSI for defect analysis by the use of the semiconductor product manufacturing line. Defect analyzing LSIs are manufactured in a predetermined number without stopping the semiconductor product manufacturing line.
The defect analyzing LSI is specially manufactured solely for defect analysis, so that the structure thereof is simple. Thus, in case a defect has taken place in the semiconductor products manufactured, this defect analyzing LSI is analyzed, whereby the specifying of the defective portion in which a defect has taken place and the clearing-up of the cause for the defect, etc. become easier as compared with the case where the actual semiconductor products are analyzed.
By the way, as the defect analyzing LSI, there is known the type which is constituted in such a manner that, shown in FIG. 19 and FIG. 20, memory cell arrays (such as SRAM cell array) 11 are formed on a chip or on the chip area of a wafer. In case of a defect analyzing LSI which has memory cell arrays, the specifying of a defective portion and the clearing-up of the cause for the defect can be more easily carried out by utilizing the so-called FBM (Fail Bit Map) system.
The FBM system mentioned here is a system constituted in such a manner that the positions of the respective memory cells in a memory cell array are represented in the form of meshes, and all the memory cells are tested, so that the position of a defective memory cell is shown in the map, whereby the specifying of the defective portion and the clearing-up of the cause for the defect are made on the basis of the disposition (category) of the defective memory cell.
The wiring structure of the defect analyzing LSI is contrived in such a manner that the disposition (categories) of defective memory cells and the defective locations or the causes for the defects correspond to each other at a rate of one to one.
Table 1 shows the relationship between the categories and the defective locations or the causes for the defects in case defect analysis is made of the defect analyzing LSI shown in FIG. 19 and FIG. 20.
The xe2x80x9ccategoryxe2x80x9d mentioned here means the disposition (pattern) of the defective memory cells detected by the defect analysis. The xe2x80x9clayerxe2x80x9d means the layer in which a defect has taken place, xe2x80x9cNode1xe2x80x9d and xe2x80x9cNode2xe2x80x9d each mean the wiring in which a defect has taken place; both the xe2x80x9clayerxe2x80x9d and xe2x80x9cNode1, 2xe2x80x9d both specify the defective locations. The xe2x80x9co/sxe2x80x9d means disconnection (open) or short-circuit (short), which specify the cause for a defect.
For example, (1) the disconnection of a word line (polycrystalline silicon layer) and (2) the disconnection of a contact plug (tungsten layer) which connects together a word line (polycrystalline layer) and a word line (first metal layer) correspond, respectively, to the disconnection of the polycrystalline silicon layer and the disconnection of a contact plug, which connects the polycrystalline silicon layer and the first metal layer to each other, in an actual semiconductor product (a logic circuit, a memory circuit or the like). However, even if the conventional defect analyzing LSI is analyzed by the use of the FBM system, these defects (disconnections) are not expressed in the form of categories.
More specifically, as shown in FIG. 21, in case of the conventional defect analyzing LSI structure, word lines (polycrystalline silicon layer) 12 and a word line (first metal layer) 13 lying above the word lines 12 both extend straight in the same direction, and they are both connected to each other at a plurality of locations by means of contact plugs 14. Further, a signal is inputted through one end of the word line (first metal layer) 13, and the other ends of the word lines (polycrystalline silicon layer, first metal layer) 12, 13 are dead ends, which are not connected to anything. Further, between the two contact plugs 14 adjacent to each other, 8 (bits) memory cells are connected to the word line (polycrystalline silicon layer) 12.
Thus, the memory cells are operated by the signal which propagates from the word line (first metal layer) 13 to the word lines (polycrystalline silicon layer) 12 via the contact plugs 14. Here, even if a disconnection has taken place in, e.g., the word lines (polycrystalline silicon layer) 12 or in the contact plugs 14, the memory cells operate without any trouble since the word lines (polycrystalline silicon layer) 12 and the word line (first metal layer) 13 are connected to each other by the plurality of contact plugs 14.
That is, as shown in FIG. 22, no category appears on the FBM, and thus, the disconnection in the word lines (polycrystalline silicon layer) and the disconnection in the contact plugs cannot be detected.
Further, in case of using a defect analyzing LSI having SRAM cell arrays (hereinafter referred to as a SRAM-TEG (Test Element Group)), the memory cells of the SRAM-TEG correspond to the memory cells formed in an actual semiconductor product (a logic circuit, a memory circuit or the like).
However, even if the conventional SRAM-TEG is analyzed by the use of the FBM system, (3) the disconnection of the contact plugs with respect to the active area (SDG area) of the SRAM cells, the disconnection of the contact plugs with respect to the polycrystalline silicon layer within the SRAM cells, and the short-circuit of the polycrystalline silicon layer within the SRAM cells all come out as belonging to utterly the same category (single-bit defect), so that these defects cannot be distinguished from one another.
More specifically, in case of the conventional SRAM-TEG structure, the respective SRAM cell (1 bit) is comprised of four MOS transistors T1 to T4 and two transfer transistors T5, T6 as shown in FIGS. 23 to 25. In FIG. 23 and FIG. 24, the transfer transistors T5, T6 are omitted. Further, in FIG. 24, the hatched portions are composed of, for example, a metal layer 1Al.
Here, the disconnection of a contact plug with respect to the active area (SDG area) of the SRAM cell, the disconnection of a contact plug with respect to the polycrystalline silicon layer within the SRAM cell, and the short-circuit of the polycrystalline silicon layer within the SRAM cell all result in disabling only one SRAM cell.
That is, even if any of the above-mentioned three types of defects has taken place, merely the category of xe2x80x9csingle-bit defectxe2x80x9d appears on the FBM as shown in FIG. 26.
As stated above, conventionally, a defect analyzing LSI is periodically manufactured separately from semiconductor products to make defect analysis on the basis of this defect analyzing LSI, but, in case of the conventional defect analyzing LSI, there is the drawback that a defect cannot be detected, or a plurality of different defects appear under the same category, so that the specifying of a defective location and the clearing-up of the cause for the defect cannot be sufficiently made.
Further, recently, in semiconductor products, the wirings thereof are becoming more and more multi-layered; for example, in case of a conventional SRAM-TEG using two-layer wirings, it is very difficult to specify all the defective locations of a semiconductor product and/or clear up the causes for all the defects.
The present invention has been made in order to solve the above-mentioned drawbacks, and it is an object of the invention to propose a defect analyzing LSI structure which can easily detect a plurality of different defects under different categories in case of periodically manufacturing a defect analyzing LSI having memory cells to make defect analysis by the use of an FBM system, whereby it becomes possible to easily specify defective locations or clear up the causes for the defects and easily effect a process feedback, thus contributing to the enhancement in the manufacturing yield of semiconductor products.
A defect analyzing semiconductor device according to the present invention comprises memory cell arrays, a plurality of first wirings disposed along a straight line in one row or one column of the memory cell arrays, a second wiring disposed above the plurality of first wirings for transmitting a signal from one end of the second wiring to the other end thereof, and a plurality of contact plugs which connect the plurality of first wirings to the second wiring, respectively, wherein the plurality of first wirings are each connected to a plurality of successive memory cells among all the memory cells in the row or the column to which the plurality of first wirings each belong.
A defect analyzing semiconductor device according to the present invention comprises memory cell arrays, a plurality of first wirings disposed along a straight line in one row or one column of the memory cell arrays, a plurality of second wirings disposed along a straight line above the plurality of first wirings, and a plurality of contact plugs which connect the plurality of first wirings and the plurality of second wirings to each other in such a manner that the plurality of first and second wirings are connected in series, wherein the plurality of first wirings are each connected to a plurality of successive memory cells among all the memory ells in one row or one column to which the plurality of first wirings each belong, and wherein a signal is transmitted from one end of the plurality of first wirings to the other end thereof.
A defect analyzing semiconductor device according to the present invention comprises memory cell arrays, two first wirings which are disposed in one column of the memory cell arrays, and to which signals complementary to each other are applied, two second wrings disposed above the two first wirings, and a plurality of contact plugs which connect one of the two first wirings to one of the two second wirings and connect the other of the two first wirings to the other of the two second wirings, wherein the two first wirings are connected to all the memory cells in the column to which the two first wirings each belong, and wherein the interval between the two first wirings is smaller than the interval between the first wiring in one of two columns adjacent to each other and the first wiring in the other column, while the interval between the two second wirings is smaller than the interval between the second wiring in one of two columns adjacent to each other and the second wiring in the other column.
A defect analyzing semiconductor device according to the present invention comprises memory cell arrays, two first wirings which are disposed in one column of the memory cell arrays and to which signals complementary to each other are applied, two second wirings disposed above or beneath the two first wirings, and a plurality of contact plugs which connect one of the two first wirings to one of the two second wirings and connect the other one of the two first wirings to the other one of the two second wirings, wherein the two first or second wirings are connected to all the memory cells in the column to which the two first or second wirings each belong, wherein the interval between the two first wirings is smaller than the interval between the first wiring in one of two columns adjacent to each other and the first wiring in the other column, while the interval between the two second wirings is larger than the interval between the second wiring in one of two columns adjacent to each other and the second wiring in the other column.
A defect analyzing semiconductor device according to the present invention comprises first and second MOS transistors which are connected in series between first and second power supplies and constitute a first inverter, third and fourth MOS transistors which are connected in series between the first and second power supplies, constitute a second inverter, and are flip-flop-connected to the first inverter, a first wiring which connects the drains of the first and second MOS transistors and the gates of the third and fourth MOS transistors to each other, and a second wiring which connects the drains of the third and fourth MOS transistors and the gates of the first and second MOS transistors to each other, wherein the contact portion between the drains of the first and second MOS transistors and the first wiring, the contact portion between the gates of the third and fourth MOS transistors and the first wiring, the contact portion between the drains of the third and fourth MOS transistor and the second wiring, and the contact portion between the gates of the first and second MOS transistors and the second wiring are each provided at two or more locations, and wherein a portion of the interval between the gates of the first and second MOS transistors and the gates of the third and fourth MOS transistors is set to a minimum work dimension.
A LSI defect analyzing method according to the present invention comprises the steps of manufacturing a semiconductor device by the use of a semiconductor product manufacturing line, forming an FBM by making tests on the memory cell arrays of the semiconductor device, and deciding that a plurality of contact plugs which connect a plurality of first wirings to a second wiring are disconnected when a plurality of successive memory cells in one row or one column are defective.
A LSI defect analyzing method according to the present invention comprises the steps of manufacturing a semiconductor device by the use of a semiconductor product manufacturing line, forming an FBM by making tests on the memory cell arrays of the semiconductor device, and deciding that a plurality of contact plugs which connect a plurality of first wirings and a plurality of second wirings to each other are disconnected when, under the assumption that a plurality of successive memory cells in one row or column constitute one unit, the memory cells n (natural number) times as many as the one unit (but the memory cells are smaller in number than all the memory cells in one row or one column) are defective.
A LSI defect analyzing method according to the present invention comprises the steps of manufacturing a semiconductor device by the use of a semiconductor product manufacturing line, forming an FBM by making tests on the memory cell arrays of the semiconductor device, and deciding that two first wirings or two second wirings are short-circuited when all the memory cells in one column are defective.
A LSI defect analyzing method according to the present invention comprises the steps of manufacturing a semiconductor device by the use of a semiconductor product manufacturing line, forming an FBM by making tests on the memory cell arrays of the semiconductor device, and deciding that the two first wirings in one column are short-circuited when all the memory cells in the one column are defective, and deciding that the two second wirings ranging over two columns which lie adjacent to each other in the row direction are short-circuited when all the memory cells in the two columns which lie adjacent to each other in the row direction are defective.
A LSI defect analyzing method according to the present invention comprises the steps of manufacturing a semiconductor device by the use of a semiconductor product manufacturing line, forming an FBM by making tests on the memory cell arrays of the semiconductor device, and deciding that a portion of the interval between the gates of first and second MOS transistors and the gates of third and fourth MOS transistors is short-circuited when a single-bit defect has taken place.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.